1. Field of the Invention
This invention relates to an information processing apparatus that adopts a virtual storage system. More particularly, the invention relates to a memory control method that constructs a virtual computer system, using a translation table indicating a correspondence between a guest virtual address and a host real address as an address translation table.
2. Description of the Related Art
A virtual storage system generally controls a correspondence between a virtual memory space and a real memory space, using the unit of block called xe2x80x9cpage.xe2x80x9d FIG. 3 shows a conception of translating a virtual address to a real address. A virtual address 310 comprises a virtual page number 311 and a page offset 312. A page table 331 is an address translation table allocated to a real memory space (main storage) 320, and the page table 331 stores real addresses (real pages) of individual virtual pages. Supposing the virtual page number is represented as xe2x80x9cn,xe2x80x9d the real address of each virtual page is stored in line 332 in the n-th location. A page table base register (PTBR) 330 indicates the real address (page table address pointer) of the page table 331, which is currently used by a processor (real computer), on the real memory space 320. By rewriting the PTBR 330, two or more page tables, i.e., two or more virtual spaces can be switched/used.
Translation from a virtual address to a real address is outlined as follows:
(1) Calculate the page table 331 on the real memory space 320 (main storage) by referring to the PTBR 330.
(2) Calculate a real page stored in the line 332 on the page table 331, depending on the virtual page number 311 in the virtual address 310.
(3) Add the page offset 312 of the virtual address 310 to the low-order bit of the real page, assuming the added real page as a real address, and access the real memory space 320, depending on the real address.
In this manner, the virtual storage system refers to the page table when calculating the real address, so the real memory needs to be accessed twice each time the virtual memory is accessed. To prevent this overhead, generally a processor contains a high-speed address translation buffer memory called xe2x80x9cTranslation Look aside Buffer (TLB)xe2x80x9d, and saves in the TLB a correspondence between a virtual page number and a real address (real page), which have been calculated by referring to the page table. If the entry of a virtual page number has been registered in the TLB, the processor searches the TLB and immediately calculates a real address from the entry, when translating the address. Only if the entry of the virtual page number has been unregistered in the TLB, the processor calculates the real address by referring to the page table on the main storage. Then, the processor newly registers the correspondence between the virtual page number and the real address (real page) in the TLB.
When the processor contains the TLB, a software controlling the virtual storage needs to invalidate the content of the TLB (called xe2x80x9cTLB purgexe2x80x9d) to avoid incorrect translation, similarly to an operating system (abbreviated xe2x80x9cOSxe2x80x9d), when the page table has been rewritten or when the page table base register (PTBR) has been rewritten. A TLB purge occurs in the following cases:
(1) When an instruction of purging a specific entry in the TLB (hereafter called xe2x80x9cEntry Purge instructionxe2x80x9d) is executed.
(2) When an instruction of writing from a program to the PTBR (hereafter called xe2x80x9cexplicit rewritexe2x80x9d) is executed.
(3) When a PTBR rewrite is executed with a task switch.
Then, a brief explanation for the task switch will be made. An information processing apparatus comprises a memory area, called xe2x80x9ctask state segment (abbreviated as TSS),xe2x80x9d for each task, where the processor status is saved when switching a task. For example, when task A is switched to task B, the processor executes the following processing:
(1) Save the register value (including a PTBR value) of the processor during executing a task switch instruction, in the task A TSS.
(2) Write a value from the task B TSS to a register in the processor.
Therefore, if the task B is switched to the task A later, the processor status before the task switch, is restored, depending on the task A TSS value saved in step (1).
On the other hand, a virtual computer system virtually operates one or more OSs on one real computer. For this system, a program called xe2x80x9chostxe2x80x9d (generally called xe2x80x9cVMCPxe2x80x9d) controls the real computer, generates one or more virtual computers (VM), and operates an independent OS (called xe2x80x9cguestxe2x80x9d) on each virtual computer. FIG. 4 shows the conception of the virtual computer system. This conception represents that OS1 and OS2 operate independently as a guest A 410 and a guest B 420 each under the control of VMCP as a host 400, and that each OS controls applications (AP).
For allocating hardware resources of a single real computer to each virtual computer, there are two methods, i.e., a method of allocating the hardware resources by time-sharing, and a method of logically dividing the hardware resources and allocating the divided resources to each virtual computer. When the virtual computer system controls a memory, the latter method is generally adopted. In this case, the host logically divides the real memory space and allocates a divided area to each guest.
FIG. 5 shows a conception of memory control performed by the virtual computer system as described above. In this embodiment, a part 541 of a real memory space 540 in the host is allocated to the guest A, and a part 542 of the real memory space 540 in the host is allocated to the guest B. Actually, the host generates a host virtual space 521 on the real memory area 541, and the guest A operates, assuming the host virtual space 521 as a real memory space (guest real space). Similarly, the host generates a host virtual space 542 on a real memory area 522, and the guest B operates, assuming the host virtual space 542 as a real memory space (guest real space). In addition, the guest A generates a guest virtual space 501, and the guest B generates a guest virtual space 502. In this case, guest translation tables (guest page tables) 511 and 512 controlled each by the guests A and B, as well as host translation tables (host page tables) 531 and 532 controlled each by the host are used as address translation tables. The guest translation tables 511 and 512 each store the guest real address (host virtual address) of each guest virtual page, and the host translation tables 531 and 532 store the host address of each host virtual page.
When the virtual computer system performs the memory control, as shown in FIG. 5, address translation is performed with the following procedure, when a processor accesses a guest virtual space. In this case, the guest virtual space of the guest A is a target to be accessed. The guest virtual space of the guest B is also accessed with the same procedure. However, an explanation for the PTBR is omitted for simplification.
(1) Translate a guest virtual address (guest virtual page) of the guest virtual space 501 to a guest real address (guest real page), i.e., a host virtual address (host virtual page) by referring to the guest translation table 511. This is called xe2x80x9cguest address translation.xe2x80x9d
(2) Translate the guest real address, i.e., the host virtual address to the host real address (host real page) by referring to the host translation table 531. This is called xe2x80x9chost address translation.xe2x80x9d This host real address indicates a physical area 541 allocated to the guest A on the real memory space 540.
When the processor comprises a TLB, the processor saves a correspondence between a guest virtual address (guest virtual page) and a host real address (host real page) in the TLB, which has been calculated by referring to a guest translation table and a host translation table. First, the processor refers to the TLB when accessing a guest virtual space. If the entry of a guest virtual page number is not found in the TLB, the processor executes two address translations, i.e., a guest address translation and a host address translation, as described above, to calculate the real address (host real address) of the real memory space (host real memory space).
When the conventional virtual computer system performs memory control, as described above, the processor executes two address translations, i.e., a guest address translation using the guest translation table (guest page table) and a host address translation using the host translation table (host page table), when accessing a guest virtual space. That is, a guest virtual address is first translated to a guest real address (=host virtual address), and secondly to a host real address.
Then, consider the case where the guest virtual address is directly translated to the host real address, focusing on that the guest virtual address is finally translated to the host real address. The conception of this address translation is shown in FIG. 6. This conception is basically the same as that shown in FIG. 3. Merely by referring to a translation table 631, the guest virtual address (guest virtual page) can be translated to the host real address (host real page). The translation table 631 is a map of addresses, which can be created.
A problem on the address translation system as shown in FIG. 6 is found in that a guest controls a guest virtual address and a host controls a real memory. For example, if the host controls the translation table 631, the content of the translation table (guest page table) rewritten by the guest may not be correctly reflected in the content of the translation table 631 (host page table).
An object of this invention is to solve the above problem, enable a table of translating a guest virtual address to a host real address to be used without a trouble, and speed up address translation by referring to a translation table when a processor accesses a guest virtual space.
According to this invention, a processor comprises a means of detecting a TLB purge, a means of detecting a PTBR read, and a means of generating an exception interrupt when the TLB purge or PTBR read is detected, so as to construct a virtual computer system using a translation table (page table) as a table of translating a guest virtual address to a host real address.
A host is invoked by an exception interrupt. When a TLB purge occurs, the host examines a virtual space change processing executed by a guest, calculates a new guest virtual address and a new host real address, and writes the correspondence between the guest virtual address and the host real address to the page table. This processing may correctly reflect the content of the virtual space changed by the guest, in the host page table. When the PTBR read is executed, the host examines the memory or register to which the guest has written a value of the PTBR and rewrites the guest virtual address to the guest real address in the guest page table. This enables the guest real address in the guest page table to be calculated when the processor accesses the guest page table using the guest PTBR.
A page table rewrite merely means a memory rewrite, which is difficult for the processor to discriminate from other memory access from other OSs except the guest OS. However, when a page table has been rewritten, the TLB content does not coincide with that of the page table, so a memory control program such as the OS necessarily executes a TLB purge. By monitoring the TLB purge, therefore, the page table rewrite may be detected indirectly. In addition, the page table change may be also detected similarly, because the TLB purge is executed at the same time when a PTBR write is executed.
Focusing on this process, this invention enables to a guest page table switch or page table entry rewrite to be detected by adding a means of monitoring a TLB purge and generating an exception to a processor.
When a guest rewrites a guest page table entry, the guest may read the PTBR. In this case, the PTBR contains the host real address, which has been set by the host, and the page table has been created by the host. Thus, a PTBR value, which is received by the guest, must be translated to a guest real address in the guest page table by monitoring the guest""s PTBR read.
Focusing on this process, this invention enables the PTBR read to be detected by adding a means of monitoring a PTBR read and generating an exception to a processor, similarly to the case where the TLB purge is monitored.
As explained above, the virtual computer system can perform memory control, by using the page table, which is controlled by the host, as a table of translating the guest virtual address to the host real address.